The invention relates generally to a method of fabricating a capacitor of a semiconductor device and, more specifically, to a method of improving a bunker defect and a short circuit phenomenon between a bit line and a lower electrode oxide pattern, which can be generated when a cylinder type capacitor having a design rule of less than 50 nm is formed.
As the demand for semiconductor memory devices increases, various techniques for obtaining a capacitor of high capacity have been suggested. The capacitor comprises a dielectric film formed between a lower electrode and an upper electrode. The capacity of the capacitor is proportional to a dielectric constant of the dielectric film and a surface area of the electrode surface, and inversely proportional to a gap between the electrodes, i.e., the thickness of the dielectric film.
In order to obtain a capacitor of high capacity, use of a dielectric film having a large dielectric constant and enlargement of the electrode surface are required. Also, it is necessary to reduce the distance between the electrodes.
However, since there is a limitation in reduction of the distance between the electrodes, i.e., the thickness of the dielectric film, a dielectric film having a large dielectric constant is used or the electrode surface is enlarged to form a capacitor of high capacity.
As shown in FIG. 1, a concave type electrode using an inner sidewall has been widely used as a lower electrode structure of the capacitor. However, as shown in FIG. 2, a cylinder type electrode using an outer sidewall as well as an inner sidewall is useful to maximize the electrode surface.
FIGS. 1 and 2 show a semiconductor substrate 1, an interlayer insulating film 2, a bit line 3, a contact plug 4, an etching barrier film 5, a lower electrode oxide film 6, a concave type lower electrode 7a, and a cylinder type lower electrode 7b. 
As the size of a dummy pattern increases when the lower electrode oxide film 6 is etched, the lower electrode oxide film 6 is over-etched rather than an inner cell pattern, so that the bit line 3 of the lower end portion and a pattern of the lower electrode oxide film 6 are interconnected to cause a short circuit phenomenon. Although the dummy pattern does not serve as a transistor, the dummy pattern improves a process margin in an exposing process.
When forming the cylinder type capacitor, a wet etching process, which is called a dip-out process, is performed to remove the lower electrode oxide film 6 (see FIG. 1) used as a frame after the lower electrode 7b is formed.
During the wet etching process, an etching solution penetrates into the lower electrode material, illustratively a TiN film, thereby causing a bunker defect where the etching solution penetrates into the etching barrier film 5, including a nitride film, and the interlayer insulating film 2, including an oxide film, which are located under the capacitor. As a result, the device reliability and the manufacturing yield are degraded.
The short circuit phenomenon and the bunker defect are generated because the size of a hole of the dummy pattern, which is the outer pattern of the layout, is enlarged when the lower electrode oxide film 6 is etched to form a pattern.
However, when the size of the dummy pattern is reduced so as to be identical with that of the cell pattern for constituting the layout, a depth of focus margin in the exposing process is reduced to less than 0.03 μm, so that there is no mass product margin. Also, the size of the hole of the cell pattern, which serves as a transistor, is affected to cause a phenomenon such that a pattern of the lower electrode oxide film 6 is not defined.